The present invention relates to integrated circuits and, more particularly, to a method of forming stacked solid vias and to structures resulting from the method. A major objective of the present invention is to provide for high density multi-chip carriers.
Much of recent technological progress is identified with the increasing miniaturization afforded by advances in integrated circuit processing technology. Dramatic improvements in the circuit density available on individual integrated circuit chips have been made. Integration of these integrated circuit chips typically requires that the chips be individually packaged and the packages mounted on printed circuit boards. The size of the packages limits the chips' density on the printed circuit board. This lack of chip density requires larger systems and limits performance due to longer connections.
More recently, multi-chip carriers have been developed which permit integrated circuit chips to be mounted on a common carrier without the need for packaging the individual chips. This allows the chips to be packed more closely together.
While multi-chip carriers have been fabricated using a variety of technologies, the greatest chip density has been achieved by multi-chip carriers fabricated using integrated circuit processing technology. In other words, a multi-chip carrier can be fabricated by photolithographically defining multiple layers of circuits interconnected by metallic vias through intermediate dielectric layers.
The vias can be formed as follows. Apertures are photolithographically defined in a dielectric layer deposited over a lower circuit layer. Vias are then formed in these apertures by sputtering or by chemical vapor deposition. Copper is the preferred via material because of its higher conductivity and current-carrying capacity but requires a distinct adhesive layer, e.g., of chromium to bond the copper to the dielectric; aluminum bonds effectively with dielectrics and for this reason is sometimes used.
The vias formed by the sputtering or chemical vapor deposition into a defined aperture are hollow. Hollow vias cannot be stacked up through successive layers because of attendant photolithographic difficulties. Specifically, a photoresist layer will follow the curvature of a hollow via surface. The resulting curvature causes deviations in the light beam used to define patterns in the photoresist; these deviations prevent certain regions of the photoresist from being exposed, and conversely, expose other regions that must not be exposed, so that the desired pattern cannot be formed.
Where interconnections are required through successive layers, the vias through individual layers are offset, forming a set of steps requiring extra space. This limits the circuit density of the carrier and thus the density with which chips can be arranged on the carrier. In addition, the less dense arrangement requires longer signal paths, which are characterized higher impedance and longer signal travel time.
What is needed is a method of fabricating a multi-chip carrier that provides for greater density in the arrangement of the integrated circuit chip carrier. More specifically, what is needed is a method of fabricating stacked vias compatible with integrated circuit processing technology.